Verilog Course Overview

6-8 Weeks Course Duration Instructor lead online interactive class Live Project and Implementations Highly Experience Certified Trainer

Our Verilog course provides a deep dive into digital design and hardware description language, ideal for aspiring hardware engineers and digital designers. In this course, you'll master the fundamentals of Verilog syntax, structural and behavioral modeling, and testbench creation for simulating digital systems.

Course Content

• Course Overview 3 lectures 15min
  Review of VLSI concepts

  04:30

  Quick CMOS basics

  09:30

  What is VLSI

  01:00
• Broad Areas in VLSI 6 lectures 45min
  VLSI Design Styles - Full custom

  10:00

  VLSI Design Styles - Semi custom

  05:00

  VLSI Design Styles - FPGA

  09:00

  VLSI Design Styles - Gate Array

  08:00

  VLSI Design Styles - Comparison

  06:45

  Full custom VS Semi custom

  05:15
• ASIC Design Flow 5 lectures 45min
  ASIC Design Flow - Part1

  05:00

  ASIC Design Flow - Part2

  20:00

  ASIC Design Flow - Design Specs

  10:00

  ASIC Design Flow - Architecturing

  05:00

  ASIC Design Flow - RTL coding

  05:00
• Fundamentals of System Verilog OOP Construct 5 lectures 45min
  Agenda

  05:00

  Ways to add method to class

  20:00

  Understanding Pass by Value

  10:00

  Understanding Pass by Reference

  05:00

  Using Array in Function

  05:00
• Randomization 5 lectures 45min
  Understanding Generator

  05:00

  Adding Constraint : Simple Expression

  20:00

  Understanding Randc Bucket

  10:00

  Understanding FIFO DUT

  05:00

  Interprocess Communication Mechanism

  05:00